The current aim is to offer the biggest memory density within the smallest possible package. Memories having a capacity of 1 Megabit housed in packages of SO8N type currently exist. The next step is to offer an SO8N package containing a memory having a capacity of 2 Megabits.
The constraint is to make the memory circuit fit into the room available in the package. Currently for a 2-Megabit memory, most of the area is occupied by the memory plane, the routing of which cannot easily be adapted as is done for the peripheral circuits. Indeed, the memories are organized into matrices with a number of rows and a number of columns equal to a power of 2. Therefore, the memory plane has a given form and the routing of the peripheral circuits is optionally done so as to adapt the form of the circuit to the desired package.
Various versions of a given package exist. They are inter alia characterized by the dimension of the metal plate at the centre of the package on which the microchip supporting the memory circuit is glued. This metal plate determines the maximum dimension of the microchip, which must be smaller than the former, with a defined minimum margin.
When the dimensions of the microchip are significant, the largest possible metal plate is chosen and one attempts to design the periphery of the memory circuit so as to adapt it to the dimension of this metal plate. It sometimes happens that the assembly rules have to be violated, or that non-standard plates are used, this often resulting in cost overrun and production and quality problems. In all cases, the margin for manoeuvre is low.
The worst case is that of memories of large capacity whose area attains the maximum area available in the package, since the X and Y dimensions of the memory plane are imposed. The low proportion of the area at the periphery with respect to the area of the memory plane thus gives little flexibility as regards the adaptation of the dimensions of the circuit to the form of the metal plate. An impossibility may then be reached.
This is all the more critical for page-programmable memories, such as for example the EEPROM memories organized into memory pages. Indeed for this type of memory, a page is the quantity of data (bytes for example) that can be programmed simultaneously. And this page constraint further limits the architecture of the memory.